From Synchronous to Asynchronous: An Automatic Approach
Proceedings of the conference on Design, automation and test in Europe - Volume 2
A clocking technique for FPGA pipelined designs
Journal of Systems Architecture: the EUROMICRO Journal
Design automation of real-life asynchronous devices and systems
Foundations and Trends in Electronic Design Automation
The design of high-performance dynamic asynchronous pipelines: lookahead style
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The design of high-performance dynamic asynchronous pipelines: high-capacity style
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automated Synchronous-to-Asynchronous Circuits Conversion: A Survey
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Application of Concurrency in the Asynchronous Design of Write-after-read Operations
Fundamenta Informaticae - Application of Concurrency to System Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Application of Concurrency in the Asynchronous Design of Write-after-read Operations
Fundamenta Informaticae - Application of Concurrency to System Design
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DLAP, an asynchronous pipeline with master-slave (dual) registers, offers improved performance. It is most suitable for converting synchronous circuits into asynchronous ones. DLAP is capable of truly decoupled operation: All pipeline stages can shift data simultaneously, and execution is faster than previous designs when variable delays are encountered. Implementations based on both edge triggered registers and transparent latches are shown. STG and verified controllers are presented and simulated.