IEEE Transactions on Computers
Reconfigurable pipelined 2-D convolvers for fast digital signal processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automatic Target Recognition with Dynamic Reconfiguration
Journal of VLSI Signal Processing Systems
Automated target recognition on SPLASH 2
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Accelerating Adobe Photoshop with the Reconfigurable Logic
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Mapping of generalized template matching onto reconfigurable computers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
An efficient hardware architecture from c program with memory access to hardware
ICCSA'10 Proceedings of the 2010 international conference on Computational Science and Its Applications - Volume Part II
Concurrency and Computation: Practice & Experience
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Image processing algorithms for 2D digital filtering, morphologic operations, motion estimation, and template matching involve massively parallel computations that can benefit from using reconfigurable systems with massive field programmable gate array (FPGA) hardware resources. In addition, each algorithm can be considered a special case of a “generalized template matching” (GTM) operation. Application performance on reconfigurable computer systems is often limited by the bandwidth to host or off chip memory. This paper describes the GTM operation and characterizes the data allocation and buffering strategies for the GTM operation on reconfigurable computers. Several mechanisms that support different levels of parallelism are proposed and summarized in the paper. Finally, the implementation of an infrared automatic target recognition application on two commercial FPGA boards is used to demonstrate the various design options with different data allocation and buffering mechanisms and the pruning of the design space based on the FPGA area and memory constraints.