The design and analysis of VLSI circuits
The design and analysis of VLSI circuits
Discrete-time signal processing
Discrete-time signal processing
How Much Logic Should Go in an FPGA Logic Block?
IEEE Design & Test
Rothko: A Three-Dimensional FPGA
IEEE Design & Test
Test methodology for a microprocessor with partial scan
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A comprehensive approach to the partial scan problem using implicit state enumeration
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Data Buffering and Allocation in Mapping Generalized Template Matching on Reconfigurable Systems
The Journal of Supercomputing
Mapping of generalized template matching onto reconfigurable computers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
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In this paper, a scan-based programmable, configurable, and scalable architecture is proposed. This architecture is suitable for a wide range of applications in signal processing requiring programmability and presenting high bandwidth and real-time requirements beyond the capacity of off-the-shelf DSPs or FGPAs. The architecture is specifically targeting a very common type of signal processing operation: sliding window operations (SWOs). Through various examples, the 驴programmability, configurability, and scalability驴 of the proposed architecture are illustrated. Our approach is then compared to traditional programmable architectures with coefficient registers in terms of gate count, speed (delay), and other implementation-related issues. This comparison reveals that our architecture leads to less complex solutions with comparable performance. In general, this approach can be seen as an alternative offering reduced recurrent costs at the expense of potentially higher nonrecurrent costs, which makes it very attractive for high volume production.