An efficient hardware architecture from c program with memory access to hardware

Authors:
Akira Yamawaki;Seiichi Serikawa;Masahiko Iwane
Affiliations:
Kyushu Institute of Technology, Kitakyushu, Japan;Kyushu Institute of Technology, Kitakyushu, Japan;Yuundo, Ltd., Japan
Venue:
ICCSA'10 Proceedings of the 2010 international conference on Computational Science and Its Applications - Volume Part II
Year:
2010

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Abstract

To improve the performance and power-consumption of the system-on-chip (SoC), the software processes are often converted to the hardware. However, to extract the performance of the hardware as much as possible, the memory access must be improved. In addition, the development period of the hardware has to be reduced because the life-cycle of SoC is commonly short. This paper proposes a design-level hardware architecture (semi-programmable hardware: SPHW) which is inserted onto the pass from C to hardware. On the SPHW, the memory accesses and buffers are realized by the software programming and parameters respectively. By using the SPHW you can easily develop the data processing hardware containing the efficient memory access controller at C-level abstraction. Compared with the conventional cases, the SPHW can reduce the development time significantly. The experimental result also shows that you can employ the SPHW as the final product if the memory access latency is hidden enough.