A Theory for Multiresolution Signal Decomposition: The Wavelet Representation
IEEE Transactions on Pattern Analysis and Machine Intelligence
High-Level Cache Modeling for 2-D Discrete Wavelet Transform Implementations
Journal of VLSI Signal Processing Systems
Discrete Wavelet Transform: Architectures, Design and Performance Issues
Journal of VLSI Signal Processing Systems
Integrated Computer-Aided Engineering
A VLSI architecture for lifting-based forward and inverse wavelettransform
IEEE Transactions on Signal Processing
Analysis and VLSI architecture for 1-D and 2-D discrete wavelet transform
IEEE Transactions on Signal Processing
Line-based, reduced memory, wavelet image compression
IEEE Transactions on Image Processing
IEEE Transactions on Image Processing
Evaluation of design alternatives for the 2-D-discrete wavelet transform
IEEE Transactions on Circuits and Systems for Video Technology
Combined line-based architecture for the 5-3 and 9-7 wavelet transform of JPEG2000
IEEE Transactions on Circuits and Systems for Video Technology
EURASIP Journal on Embedded Systems - Special issue on design and architectures for signal and image processing
Prediction-based incremental refinement for binomially-factorized discrete wavelet transforms
IEEE Transactions on Signal Processing
International Journal of Sensor Networks
An efficient hardware architecture from c program with memory access to hardware
ICCSA'10 Proceedings of the 2010 international conference on Computational Science and Its Applications - Volume Part II
A Unified FPGA-Based System Architecture for 2-D Discrete Wavelet Transform
Journal of Signal Processing Systems
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The suitability of the 2D Discrete Wavelet Transform (DWT) as a tool in image and video compression is nowadays indisputable. For the execution of the multilevel 2D DWT, several computation schedules based on different input traversal patterns have been proposed. Among these, the most commonly used in practical designs are: the row---column, the line-based and the block-based. In this work, these schedules are implemented on FPGA-based platforms for the forward 2D DWT by using a lifting-based filter-bank implementation. Our designs were realized in VHDL and optimized in terms of throughput and memory requirements, in accordance with the principles of both the schedules and the lifting decomposition. The implementations are fully parameterized with respect to the size of the input image and the number of decomposition levels. We provide detailed experimental results concerning the throughput, the area, the memory requirements and the energy dissipation, associated with every point of the parameter space. These results demonstrate that the choice of the suitable schedule is a decision that should be dependent on the given algorithmic specifications.