Journal of Signal Processing Systems
New approach to orthogonal multiplierless wavelet family synthesis
WAV'08 Proceedings of the 2nd WSEAS International Conference on Wavelets Theory and Applications in Applied Mathematics, Signal Processing and Modern Science
Finding and Applying Loop Transformations for Generating Optimized FPGA Implementations
Transactions on High-Performance Embedded Architectures and Compilers I
Multimode embedded compression codec engine for power-aware video coding system
IEEE Transactions on Circuits and Systems for Video Technology
A pipeline VLSI architecture for high-speed computation of the 1-D discrete wavelet transform
IEEE Transactions on Circuits and Systems Part I: Regular Papers
FPGA implementation of multiplierless 5/3 LeGall discrete wavelet transform using lifting approach
Proceedings of the International Conference & Workshop on Emerging Trends in Technology
Realization of wavelet transform using switched-current filters
Analog Integrated Circuits and Signal Processing
| Hi-index | 35.68 |
In this paper, a detailed analysis of very large scale integration (VLSI) architectures for the one-dimensional (1-D) and two-dimensional (2-D) discrete wavelet transform (DWT) is presented in many aspects, and three related architectures are proposed as well. The 1-D DWT and inverse DWT (IDWT) architectures are classified into three categories: convolution-based, lifting-based, and B-spline-based. They are discussed in terms of hardware complexity, critical path, and registers. As for the 2-D DWT, the large amount of the frame memory access and the die area occupied by the embedded internal buffer become the most critical issues. The 2-D DWT architectures are categorized and analyzed by different external memory scan methods. The implementation issues of the internal buffer are also discussed, and some real-life experiments are given to show that the area and power for the internal buffer are highly related to memory technology and working frequency, instead of the required memory size only. Besides the analysis, the B-spline-based IDWT architecture and the overlapped stripe-based scan method are also proposed. Last, we propose a flexible and efficient architecture for a one-level 2-D DWT that exploits many advantages of the presented analysis.