Discrete Wavelet Transform: Architectures, Design and Performance Issues

Authors:
Michael Weeks;Magdy Bayoumi
Affiliations:
Department of Computer Science, Georgia State University, Atlanta, Georgia 30303;Center for Advanced Computer Studies, University of Louisiana at Lafayette, Lafayette, Louisiana 70504
Venue:
Journal of VLSI Signal Processing Systems
Year:
2003

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Abstract

Due to the demand for real time wavelet processors in applications such as video compression [1], Internet communications compression [2], object recognition [3], and numerical analysis, many architectures for the Discrete Wavelet Transform (DWT) systems have been proposed. This paper surveys the different approaches to designing DWT architectures. The types of architectures depend on whether the application is 1-D, 2-D, or 3-D, as well as the style of architecture: systolic, semi-systolic, folded, digit-serial, etc. This paper presents an overview and evaluation of the architectures based on the criteria of latency, control, area, memory, and number of multipliers and adders. This paper will give the reader an indication of the advantages and disadvantages of each design.