Non-Memory-Based and Real-Time Zerotree Building for Wavelet Zerotree Coding Systems
IPDPS '00 Proceedings of the 15 IPDPS 2000 Workshops on Parallel and Distributed Processing
Novel JPEG 2000 Compliant DWT and IWT VLSI Implementations
Journal of VLSI Signal Processing Systems
Discrete Wavelet Transform: Architectures, Design and Performance Issues
Journal of VLSI Signal Processing Systems
A Novel FPGA Architecture of a 2-D Wavelet Transform
Journal of VLSI Signal Processing Systems
Efficient VLSI architectures for convolution and lifting based 2-d discrete wavelet transform
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
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This paper presents the architecture and implementation of a single-chip VLSI for the two-dimensional discrete wavelet transform (2-D DWT) decomposition. This nonseparable based architecture uses a parallel-systolic filter structure to compute all the resolution levels of the DWTs, such that the input samples can be processed at the rate of one sample per clock cycle. The chip was fabricated in a 0.6 μm CMOS technology and packaged as a 48-pin DIP. For the computation of an N×N still image with a filter length L, this chip needs N2 +N clock cycles and N(2L-1) memory storage; for continuous picture such as video signal, its average computation time per picture is about N2 only