Efficient VLSI architectures for convolution and lifting based 2-d discrete wavelet transform

Authors:
Gab Cheon Jung;Seong Mo Park;Jung Hyoun Kim
Affiliations:
Dept. of Electronics Engineering, Chonnam National University, Gwangju, Korea;Dept. of Computer Engineering, Chonnam National University, Gwangju, Korea;Dept. of Electrical Engineering, North Carolina A&T State University, Greensboro, NC
Venue:
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
Year:
2005

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Abstract

This paper presents efficient VLSI architectures for real time processing of separable convolution and lifting based 2-D discrete wavelet transform (DWT). Convolution based architecture uses partitioning algorithm based on the state space representation method and lifting based architecture applies pipelining to each lifting step. Both architectures use recursive pyramid algorithm(RPA) scheduling that intersperses both the row and column operations of the second and following levels among column operations of the first level without using additional filter for row operations of the second and following levels. As a result, proposed architectures have smaller hardware complexity compared to that of other conventional separable architectures with comparable throughput.