A Novel FPGA Architecture of a 2-D Wavelet Transform

Authors:
Ricardo José Palero;Rafael Gadea Gironés;Angel Sebastia Cortes
Affiliations:
Digital Systems Design Research Team, Department of Electronic Engineering, Polytechnic University of Valencia, Valencia, Spain 46022;Digital Systems Design Research Team, Department of Electronic Engineering, Polytechnic University of Valencia, Valencia, Spain 46022;Digital Systems Design Research Team, Department of Electronic Engineering, Polytechnic University of Valencia, Valencia, Spain 46022
Venue:
Journal of VLSI Signal Processing Systems
Year:
2006

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Abstract

This paper presents a new architecture for implementing a two-dimensional Discrete Wavelet Transform (2-D DWT). This architecture works in a non-separable fashion using a parallel filter structure with distributed control to compute all the DWT resolution levels. The architecture is modular and scalable in its totality. In this way, the input sample can be processed at the rate of one sample per clock cycle. To compute an N 脳 N still image with a filter length L, N2驴+驴N clock cycles and 4.5N memory storage cells are required. Implementation results based on a Xilinx Virtex FPGA device are included.