A Theory for Multiresolution Signal Decomposition: The Wavelet Representation
IEEE Transactions on Pattern Analysis and Machine Intelligence
A Novel FPGA Architecture of a 2-D Wavelet Transform
Journal of VLSI Signal Processing Systems
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This paper reports an efficient implementation of the Discrete Wavelet Packet Transform with hardware acceleration. This design relies on the implementation of the word-serial pipeline architecture and filter parallelism to minimize the processing time and maximize performance. The acceleration, working two times faster than Architecture reported in [9] is achieved by designing parallel high-pass and low-pass filters at each tree level using internal FPGA multipliers. The architecture can be implemented for any filter with different orders. The performance evaluation is made with the AT2 figure of merit. The results show that the implementation reported provides an AT2 figure that is consistently smaller than 0.5 outperforming previous implementations reported in [9]. This high speed architecture can be used to implement the Direct Wavelet Packet Transform at any tree level and is suitable for real-time applications.