A Theory for Multiresolution Signal Decomposition: The Wavelet Representation
IEEE Transactions on Pattern Analysis and Machine Intelligence
VLSI architecture for fast 2D discrete orthonormal wavelet transform
Journal of VLSI Signal Processing Systems
Digital Video and HDTV Algorithms and Interfaces
Digital Video and HDTV Algorithms and Interfaces
Discrete Wavelet Transform: Architectures, Design and Performance Issues
Journal of VLSI Signal Processing Systems
IEEE Transactions on Signal Processing
Two fast architectures for the direct 2-D discrete wavelettransform
IEEE Transactions on Signal Processing
The wavelet transform, time-frequency localization and signal analysis
IEEE Transactions on Information Theory
Nonseparable multidimensional perfect reconstruction filter banks and wavelet bases for Rn
IEEE Transactions on Information Theory - Part 2
Tomographic reconstruction using nonseparable wavelets
IEEE Transactions on Image Processing
Combined line-based architecture for the 5-3 and 9-7 wavelet transform of JPEG2000
IEEE Transactions on Circuits and Systems for Video Technology
Grey video compression methods using fractals
International Journal of Computer Mathematics - Celebrating the Life of David J. Evans
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Recent advances in image analysis have shown that the application of 2-D discrete biorthogonal wavelet transform (DBWT) to digital image compression overcomes some of the barriers imposed by block-based transform coding algorithms while offering significant advantages in terms of coding gain, quality, natural compatibility with video formats requiring lower-resolution and graceful performance degradation when compressing at low bit rates. This paper reports on the design and field programmable gate array (FPGA) implementation of a non-separable 2-D DBWT architecture which is the heart of the proposed high-definition television (HDTV) compression system. The architecture adopts periodic symmetric extension at the image boundaries, therefore it conforms the JPEG-2000 standard. It computes the DBWT decomposition of an NxN image in approximately 2N^2/3 clock cycles (ccs). Hardware implementation results based on a Xilinx Virtex-2000E FPGA chip showed that the processing of 2-D DBWT can be performed at 105MHz providing a complete solution for the real-time computation of 2-D DBWT for HDTV compression.