Coordinated parallelizing compiler optimizations and high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An FPGA-based VLIW processor with custom hardware execution
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Software thread integration for embedded system display applications
ACM Transactions on Embedded Computing Systems (TECS)
An efficient and versatile scheduling algorithm based on SDC formulation
Proceedings of the 43rd annual Design Automation Conference
Hand-in-hand verification of high-level synthesis
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Data-flow transformations using Taylor expansion diagrams
Proceedings of the conference on Design, automation and test in Europe
EURASIP Journal on Applied Signal Processing
Optimization of data-flow computations using canonical TED representation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hardware/software codesign for embedded implementation of neural networks
ARC'07 Proceedings of the 3rd international conference on Reconfigurable computing: architectures, tools and applications
Verification of datapath and controller generation phase in high-level synthesis of digital circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimizing data flow graphs to minimize hardware implementation
Proceedings of the Conference on Design, Automation and Test in Europe
Register pressure aware scheduling for high level synthesis
Proceedings of the 16th Asia and South Pacific Design Automation Conference
High performance and area efficient flexible DSP datapath synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An efficient hardware architecture from c program with memory access to hardware
ICCSA'10 Proceedings of the 2010 international conference on Computational Science and Its Applications - Volume Part II
Formal verification of code motion techniques using data-flow-driven equivalence checking
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
Translation validation for PRES+ models of parallel behaviours via an FSMD equivalence checker
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
Compiler-in-the-loop exploration during datapath synthesis for higher quality delay-area trade-offs
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
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The quality of synthesis results for most high-level synthesis approaches is strongly affected by the choice of control flow (through conditions and loops) in the input description. This leads to a need for high-level and compiler transformations that overcome the effects of programming style on the quality of generated circuits. To address this issue, we have developed a set of speculative code-motion transformations that enable movement of operations through, beyond, and into conditionals with the objective of maximizing performance. We have implemented these code transformations, along with supporting code-motion techniques and variable renaming techniques, in a high-level synthesis research framework called Spark. Spark takes a behavioral description in ANSI-C as input and generates synthesizable register-transfer level VHDL. We present results for experiments on designs derived from three real-life multimedia and image processing applications, namely, the MPEG-1 and -2 and GNU image manipulation program applications. We find that the speculative-code motions lead to reductions between 36% and 59% in the number of states in the finite-state machine (controller complexity) and the cycles on the longest path (performance) compared with the case when only nonspeculative code motions are employed. Also, logic synthesis results show fairly constant critical path lengths (clock period) and a marginal increase in area.