Digital VLSI for neural networks
The handbook of brain theory and neural networks
Neural Computation
FPGA-targeted neural architecture for embedded alertness detection
AIA'06 Proceedings of the 24th IASTED international conference on Artificial intelligence and applications
Parallel programming models for a multiprocessor SoC platform applied to networking and multimedia
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Overview of a compiler for synthesizing MATLAB programs onto FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2002 international symposium on low-power electronics and design (ISLPED)
Using global code motions to improve the quality of results for high-level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Elementary function generators for neural-network emulators
IEEE Transactions on Neural Networks
Implementation issues of neuro-fuzzy hardware: going toward HW/SW codesign
IEEE Transactions on Neural Networks
Implementation of Central Pattern Generator in an FPGA-Based Embedded System
ICANN '08 Proceedings of the 18th international conference on Artificial Neural Networks, Part II
Biologically-Inspired Digital Architecture for a Cortical Model of Orientation Selectivity
ICANN '08 Proceedings of the 18th international conference on Artificial Neural Networks, Part II
A Hardware Accelerated Simulation Environment for Spiking Neural Networks
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
Hardware implementation of a CPG-based locomotion control for quadruped robots
ICANN'10 Proceedings of the 20th international conference on Artificial neural networks: Part II
A Comparison Study for a Neural Network Based Embedded Appliance
Proceedings of the 2011 conference on Neural Nets WIRN10: Proceedings of the 20th Italian Workshop on Neural Nets
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The performance of configurable digital circuits such as Field Programmable Gate Arrays (FPGA) increases at a very fast rate. Their fine-grain parallelism shows great similarities with connectionist models. This is the motivation for numerous works of neural network implementations on FPGAs, targeting applications such as autonomous robotics, ambulatory medical systems, etc. Nevertheless, such implementations are performed with an ASPC (Application-Specific Programmable Circuits) approach that requires a strong hardware expertise. In this paper a high-level design framework for FPGA-based implementations of neural networks from high level specifications is presented but the final goal of the project is a hardware/software codesign environment for embedded implementations of most classical neural topologies. Such a framework aims at providing the connectionist community with efficient automatic FPGA implementations of their models without any advanced knowledge of hardware. A current developed software platform, NNetWARE-Builder, handles multilayer feedforward and graphically-designed neural networks and automatically compiles them onto FPGA devices with third party synthesis tools. The internal representation of a neural model is bound to commonly used hardware computing units in a library to create the hardware model. Experimental results are presented to evaluate design and implementation tradeoffs.