Hardware/software codesign for embedded implementation of neural networks
ARC'07 Proceedings of the 3rd international conference on Reconfigurable computing: architectures, tools and applications
Reconfigurable hardware evolution platform for a spiking neural network robotics controller
ARC'07 Proceedings of the 3rd international conference on Reconfigurable computing: architectures, tools and applications
Adaptive co-ordinate transformation based on a spike timing-dependent plasticity learning paradigm
ICNC'05 Proceedings of the First international conference on Advances in Natural Computation - Volume Part I
A novel approach for the implementation of large scale spiking neural networks on FPGA hardware
IWANN'05 Proceedings of the 8th international conference on Artificial Neural Networks: computational Intelligence and Bioinspired Systems
Dynamically Reconfigurable Silicon Array of Spiking Neurons With Conductance-Based Synapses
IEEE Transactions on Neural Networks
IEEE Transactions on Neural Networks
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Spiking Neural Networks (SNNs) model the biological functions of the human brain enabling neuro/computer scientists to investigate how arrays of neurons can be used to solve computational tasks. However, as network models approach the biological scale with significantly large numbers of neurons, existing software simulation environments face the problem of scalability and increasing simulation times. Emulation in hardware offers a significant increase in the acceleration of simulations through the exploitation of parallelism and dedicated on-chip training. However, it is important that the configuration of SNNs for hardware emulation is abstracted from the novice end-user to allow flexible, high-level specification and execution. This paper presents a novel reconfigurable hardware architecture and internet-based configuration environment for the FPGA-based acceleration of SNNs with online training. Results are presented to demonstrate the acceleration performance.