FPGA-based configurable systolic architecture for window-based image processing
EURASIP Journal on Applied Signal Processing
Computer
Hardware/software codesign for embedded implementation of neural networks
ARC'07 Proceedings of the 3rd international conference on Reconfigurable computing: architectures, tools and applications
The Impact of Arithmetic Representation on Implementing MLP-BP on FPGAs: A Study
IEEE Transactions on Neural Networks
IEEE Transactions on Neural Networks
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This paper presents a biologically inspired modular hardware implementation of a cortical model of orientation selectivity of the visual stimuli in the primary visual cortex targeted to a Field Programmable Gate Array (FPGA) device. The architecture mimics the functionality and organization of neurons through spatial Gabor-like filtering and the so-called cortical hypercolumnar organization. A systolic array and a suitable image addressing scheme are used to partially overcome the von Neumann bottleneck of monolithic memory organization in conventional microprocessor-based system by processing small and local amounts of sensory information (image tiles) in an incremental way. A real-time FPGA implementation is presented for 8 different orientations and aspects such as flexibility, scalability, performance and precision are discussed to show the plausibility of implementing biologically-inspired processing for early visual perception in digital devices.