Machine vision
Field-programmable gate arrays
Communications of the ACM
A high level FPGA-based abstract machine for processing
Journal of Systems Architecture: the EUROMICRO Journal - Special issue on parallel image proccesing (PIP)
Reconfigurable pipelined 2-D convolvers for fast digital signal processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computers
VLSI and Parallel Computing for Pattern Recognition and Artificial Intelligence
VLSI and Parallel Computing for Pattern Recognition and Artificial Intelligence
Real-Time Imaging: Theory, Techniques, and Application
Real-Time Imaging: Theory, Techniques, and Application
Computer Vision
Compiling and Optimizing Image Processing Algorithms for FPGAs
CAMP '00 Proceedings of the Fifth IEEE International Workshop on Computer Architectures for Machine Perception (CAMP'00)
Computer vision algorithms on reconfigurable logic arrays
Computer vision algorithms on reconfigurable logic arrays
Biologically-Inspired Digital Architecture for a Cortical Model of Orientation Selectivity
ICANN '08 Proceedings of the 18th international conference on Artificial Neural Networks, Part II
Best-Shot Selection for Video Face Recognition Using FPGA
CIARP '08 Proceedings of the 13th Iberoamerican congress on Pattern Recognition: Progress in Pattern Recognition, Image Analysis and Applications
Real Time Hot Spot Detection Using FPGA
CIARP '09 Proceedings of the 14th Iberoamerican Conference on Pattern Recognition: Progress in Pattern Recognition, Image Analysis, Computer Vision, and Applications
Experiencing a problem-based learning approach for teaching reconfigurable architecture design
International Journal of Reconfigurable Computing - Selected papers from ReCoSoc08
A design space exploration algorithm in compiling window operation onto reconfigurable hardware
International Journal of Computers and Applications
Parameterized hardware design on reconfigurable computers: an image processing case study
International Journal of Reconfigurable Computing - Special issue on selected papers from spl 2009 programmable logic and applications
FPGA-based architecture for the real-time computation of 2-D convolution with large kernel size
Journal of Systems Architecture: the EUROMICRO Journal
Real-time video surveillance on an embedded, programmable platform
Microprocessors & Microsystems
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Image processing requires more computational power and data throughput than most conventional processors can provide. Designing specific hardware can improve execution time and achieve better performance per unit of silicon area. A field-programmable-gate-array- (FPGA-) based configurable systolic architecture specially tailored for real-time window-based image operations is presented in this paper. The architecture is based on a 2D systolic array of 7×7 configurable window processors. The architecture was implemented on an FPGA to execute algorithms with window sizes up to 7×7, but the design is scalable to cover larger window sizes if required. The architecture reaches a throughput of 3.16 GOPs at a 60 MHz clock frequency and a processing time of 8.35 milliseconds for 7×7 generic window-based operators on 512×512 gray-level images. The architecture compares favorably with other architectures in terms of performance and hardware utilization. Theoretical and experimental results are presented to demonstrate the architecture effectiveness.