Algorithmic transformations in the implementation of K- means clustering on reconfigurable hardware
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
FPGA-based configurable systolic architecture for window-based image processing
EURASIP Journal on Applied Signal Processing
Rigid molecule docking: FPGA reconfiguration for alternative force laws
EURASIP Journal on Applied Signal Processing
Synthesis of multi-dimensional high-speed FIFOs for out-of-order communication
ARCS'08 Proceedings of the 21st international conference on Architecture of computing systems
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This paper presents a high-level language for expressing image processing algorithms, and an optimizing compiler that targets FPGAs. The language is called SA-C, and this paper focuses on the language features that 1) support image processing, and 2) enable efficient compilation to FPGAs. It then describes the compilation process, in which SA-C algorithms are translated into non-recursive data flow graphs, which in turn are translated into VHDL. Finally, it presents performance numbers for some well-known image processing routines, written in SAC and automatically compiled to an Annapolis Microsystems WildForce board with Xilinx 4036XL FPGAs.