On the exponential value of labeled samples
Pattern Recognition Letters
Compiling and Optimizing Image Processing Algorithms for FPGAs
CAMP '00 Proceedings of the Fifth IEEE International Workshop on Computer Architectures for Machine Perception (CAMP'00)
Stream-Oriented FPGA Computing in the Streams-C High Level Language
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
A MATLAB Compiler for Distributed, Heterogeneous, Reconfigurable Computing Systems
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
A Library of Parameterized Floating-Point Modules and Their Use
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Experience with a Hybrid Processor: K-Means Clustering
The Journal of Supercomputing
Polymorphous fabric-based systems: model, tools, applications
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable systems
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Quantization Error and Accuracy-Performance Tradeoffs for Embedded Data Mining Workloads
ICCS '07 Proceedings of the 7th international conference on Computational Science, Part III: ICCS 2007
Efficient K-Means VLSI Architecture for Vector Quantization
SCIA '09 Proceedings of the 16th Scandinavian Conference on Image Analysis
High speed c-means clustering in reconfigurable hardware
Microprocessors & Microsystems
Bandwidth adaptive hardware architecture of K-Means clustering for video analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Active storage networks for accelerating K-means data clustering
ARC'11 Proceedings of the 7th international conference on Reconfigurable computing: architectures, tools and applications
Perspectives of self-adapted self-organizing clustering in organic computing
BioADIT'06 Proceedings of the Second international conference on Biologically Inspired Approaches to Advanced Information Technology
Incremental clustering applied to radar deinterleaving: a parameterized FPGA implementation
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
ACM Transactions on Architecture and Code Optimization (TACO) - Special Issue on High-Performance Embedded Architectures and Compilers
International Journal of Reconfigurable Computing - Special issue on Selected Papers from the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2011)
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In mapping the k-means algorithm to FPGA hardware, we examined algorithm level transforms that dramatically increased the achievable parallelism. We apply the k-means algorithm to multi-spectral and hyper-spectral images, which have tens to hundreds of channels per pixel of data. K-means is an iterative algorithm that assigns assigns to each pixel a label indicating which of K clusters the pixel belongs to.K-means is a common solution to the segmentation of multi-dimensional data. The standard software implementation of k-means uses floating-point arithmetic and Euclidean distances. Floating point arithmetic and the multiplication-heavy Euclidean distance calculation are fine on a general purpose processor, but they have large area and speed penalties when implemented on an FPGA. In order to get the best performance of k-means on an FPGA, the algorithm needs to be transformed to eliminate these operations. We examined the effects of using two other distance measures, Manhattan and Max, that do not require multipliers. We also examined the effects of using fixed precision and truncated bit widths in the algorithm.It is important to explore algorithmic level transforms and tradeoffs when mapping an algorithm to reconfigurable hardware. A direct translation of the standard software implementation of k-means would result in a very inefficient use of FPGA hardware resources. Analysis of the algorithm and data is necessary for a more efficient implementation. Our resulting implementation exhibits approximately a 200 times speed up over a software implementation.