Programmable active memories: reconfigurable systems come of age
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Algorithmic transformations in the implementation of K- means clustering on reconfigurable hardware
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
A Polymorphous Computing Fabric
IEEE Micro
RaPiD - Reconfigurable Pipelined Datapath
FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
Garp: a MIPS processor with a reconfigurable coprocessor
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
JHDL - An HDL for Reconfigurable Systems
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
A Quantitative Analysis of Reconfigurable Coprocessors for Multimedia Applications
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Experience with a Hybrid Processor: K-Means Clustering
The Journal of Supercomputing
Journal of Systems Architecture: the EUROMICRO Journal
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
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A polymorphous fabric-based systems is a parameterized cellular architecture in which an array of computing cells communicates with an embedded processor through a global memory. This architecture is customizable to different classes of applications by functional unit, interconnect, and memory parameters, and can be instantiated efficiently on platform FPGAs. In previous work [IEEE Micro 22(5) (2002)], we have demonstrated the advantage of reconfigurable fabrics for image and signal processing applications. Recently, we have build a fabric generator (FG), a Java-based toolset that greatly accelerates construction of the fabrics. A module-generation library is used to define, instantiate, and interconnect cells' datapaths. FG also generates customized sequencers for individual cells or collections of cells. We describe the fabric-based system model, the FG toolset, and concrete realizations of fabric architectures generated by FG on the Altera Excalibur ARM that can deliver 4.5 GigaMACs/s (8/16 bit data, multiply-accumulate).