Efficient K-Means VLSI Architecture for Vector Quantization

Authors:
Hui-Ya Li;Wen-Jyi Hwang;Chih-Chieh Hsu;Chia-Lung Hung
Affiliations:
Department of Computer Science and Information Engineering, National Taiwan Normal University, Taipei, Taiwan 117;Department of Computer Science and Information Engineering, National Taiwan Normal University, Taipei, Taiwan 117;Department of Computer Science and Information Engineering, National Taiwan Normal University, Taipei, Taiwan 117;Department of Computer Science and Information Engineering, National Taiwan Normal University, Taipei, Taiwan 117
Venue:
SCIA '09 Proceedings of the 16th Scandinavian Conference on Image Analysis
Year:
2009

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Abstract

A novel hardware architecture for k -means clustering is presented in this paper. Our architecture is fully pipelined for both the partitioning and centroid computation operations so that multiple training vectors can be concurrently processed. The proposed architecture is used as a hardware accelerator for a softcore NIOS CPU implemented on a FPGA device for physical performance measurement. Numerical results reveal that our design is an effective solution with low area cost and high computation performance for k -means design.