Vector quantization and signal compression
Vector quantization and signal compression
Hardware architecture for genetic algorithms
IEA/AIE'2005 Proceedings of the 18th international conference on Innovations in Applied Artificial Intelligence
Efficient K-Means VLSI Architecture for Vector Quantization
SCIA '09 Proceedings of the 16th Scandinavian Conference on Image Analysis
Hi-index | 0.00 |
A novel parallel memetic algorithm (MA) architecture for the design of vector quantizers is presented in this paper The architecture contains a number of modules operating memetic optimization concurrently Each module uses steady-state genetic algorithm (GA) for global search, and K-means algorithm for local refinement A shift register based circuit for accelerating mutation and crossover operations for steady state GA operations is adopted in the design A pipeline architecture for the hardware implementation of K-means algorithm is also used The proposed architecture is embedded in a softcore CPU, and implemented on a field programmable logic array (FPGA) device for physical performance measurement.