Vector quantization and signal compression
Vector quantization and signal compression
ACM Computing Surveys (CSUR)
Introduction to data compression (2nd ed.)
Introduction to data compression (2nd ed.)
Algorithmic transformations in the implementation of K- means clustering on reconfigurable hardware
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
FPGA Architectural Research: A Survey
IEEE Design & Test
Experience with a Hybrid Processor: K-Means Clustering
The Journal of Supercomputing
Hyperspectral Images Clustering on Reconfigurable Hardware Using the K-Means Algorithm
SBCCI '03 Proceedings of the 16th symposium on Integrated circuits and systems design
Real-time K-Means Clustering for Color Images on Reconfigurable Hardware
ICPR '06 Proceedings of the 18th International Conference on Pattern Recognition - Volume 02
FPGA implementation of full-search vector quantization based on partial distance search
Microprocessors & Microsystems
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
A new VLSI architecture for full-search vector quantization
IEEE Transactions on Circuits and Systems for Video Technology
Modular VLSI architectures for real-time full-search-based vector quantization
IEEE Transactions on Circuits and Systems for Video Technology
Digital implementation of hierarchical vector quantization
IEEE Transactions on Neural Networks
Incremental clustering applied to radar deinterleaving: a parameterized FPGA implementation
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Hi-index | 0.00 |
A novel hardware architecture for c-means clustering is presented in this paper. Our architecture is fully pipelined for both the partitioning and centroid computation operations so that multiple training vectors can be concurrently processed. A simple divider circuit based on lookup table, multiplication and shift operations is employed for reducing both the area cost and latency for centroid computation. The proposed architecture is used as a hardware accelerator for a softcore NIOS CPU implemented on an FPGA device for physical performance measurement. Numerical results reveal that our design is an effective solution with low area cost and high computation performance for c-means design.