Mlp neural network and on-line backpropagation learning implementation in a low-cost fpga
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Biologically-Inspired Digital Architecture for a Cortical Model of Orientation Selectivity
ICANN '08 Proceedings of the 18th international conference on Artificial Neural Networks, Part II
IEEE Transactions on Neural Networks
Realizing general MLP networks with minimal FPGA resources
IJCNN'09 Proceedings of the 2009 international joint conference on Neural Networks
LambdaRank acceleration for relevance ranking in web search engines (abstract only)
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Digital Signal Processing
A mixed hardware-software approach to flexible artificial neural network training on FPGA
SAMOS'09 Proceedings of the 9th international conference on Systems, architectures, modeling and simulation
A dynamically configurable coprocessor for convolutional neural networks
Proceedings of the 37th annual international symposium on Computer architecture
IEEE Transactions on Neural Networks
High-performance reconfigurable hardware architecture for restricted Boltzmann machines
IEEE Transactions on Neural Networks
An FPGA-based accelerator for LambdaRank in Web search engines
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
A scalable pipelined architecture for real-time computation of MLP-BP neural networks
Microprocessors & Microsystems
Neural identification of dynamic systems on FPGA with improved PSO learning
Applied Soft Computing
On the objective function and learning algorithm for concurrent open node fault
ICONIP'12 Proceedings of the 19th international conference on Neural Information Processing - Volume Part III
International Journal of High Performance Systems Architecture
Hi-index | 0.00 |
In this paper, arithmetic representations for implementing multilayer perceptrons trained using the error backpropagation algorithm (MLP-BP) neural networks on field-programmable gate arrays (FPGAs) are examined in detail. Both floating-point (FLP) and fixed-point (FXP) formats are studied and the effect of precision of representation and FPGA area requirements are considered. A generic very high-speed integrated circuit hardware description language (VHDL) program was developed to help experiment with a large number of formats and designs. The results show that an MLP-BP network uses less clock cycles and consumes less real estate when compiled in an FXP format, compared with a larger and slower functioning compilation in an FLP format with similar data representation width, in bits, or a similar precision and range