A Computational Approach to Edge Detection
IEEE Transactions on Pattern Analysis and Machine Intelligence
Segmentation of ultrasound images by using a hybrid neural network
Pattern Recognition Letters
Face recognition using point symmetry distance-based RBF network
Applied Soft Computing
Hand geometry identification without feature extraction by general regression neural network
Expert Systems with Applications: An International Journal
Expert Systems with Applications: An International Journal
Hardware implementation of pulse mode RBF neural network-based image denoising
International Journal of Innovative Computing and Applications
FPGA implementation of a wavelet neural network with particle swarm optimization learning
Mathematical and Computer Modelling: An International Journal
IEEE Transactions on Neural Networks
A digital hardware pulse-mode neuron with piecewise linear activation function
IEEE Transactions on Neural Networks
A general regression neural network
IEEE Transactions on Neural Networks
The Impact of Arithmetic Representation on Implementing MLP-BP on FPGAs: A Study
IEEE Transactions on Neural Networks
IEEE Transactions on Neural Networks
Random noise effects in pulse-mode digital multilayer neural networks
IEEE Transactions on Neural Networks
Two digital circuits for a fully parallel stochastic neural network
IEEE Transactions on Neural Networks
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A key task in the hardware implementation of neural networks is the design of activation functions. We focus in this paper on hardware driven simple implementation of a bell-shaped function BSF avoiding complexity and reducing hardware resources with efficient on-chip learning. This implementation is done in pulse mode to take advantage of its valuable features, significantly reducing the hardware cost. The proposed design is flexible and scalable enabling several image processing potential tasks. A first application is devoted to image denoising where a comparison with some existing denoising techniques demonstrates the efficiency of the proposed approach. As a second application, we consider edge detection operation and good approximation features are accordingly obtained. The corresponding design is implemented on a Virtex-II-PRO FPGA platform. Synthesis results prove that the bell-shaped PMNN is not cumbersome, and provides higher performances versus other PMNN architectures in terms of computing speed and required hardware resources.