Elastic Neural Net Algorithm for Cluster Analysis
SBRN '00 Proceedings of the VI Brazilian Symposium on Neural Networks (SBRN'00)
Fault tolerance of switch blocks and switch block arrays in FPGA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A gradual neural network approach for FPGA segmented channelrouting problems
IEEE Transactions on Systems, Man, and Cybernetics, Part B: Cybernetics
Real-time face detection and lip feature extraction using field-programmable gate arrays
IEEE Transactions on Systems, Man, and Cybernetics, Part B: Cybernetics
A general regression neural network
IEEE Transactions on Neural Networks
The Impact of Arithmetic Representation on Implementing MLP-BP on FPGAs: A Study
IEEE Transactions on Neural Networks
An incremental probabilistic neural network for regression and reinforcement learning tasks
ICANN'10 Proceedings of the 20th international conference on Artificial neural networks: Part II
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This study proposes an approach to implement a General Regression Neural Network (GRNN) based on Field Programmable Gate Array (FPGA). The GRNN has a four-layer structure which is comprised of an input layer, a pattern layer, a summation layer and an output layer. The layers of GRNN are designed with fixed-point arithmetic using synthesizable VHDL (Very High Speed Integrated Circuit Hardware Description Language) code for FPGA implementation. In this work, the system was designed for pattern classification applications; however, it can be used for other application areas of GRNN. Different datasets were used to test the GRNN. Simulation results show that pattern classification by hardware implementation of GRNN has successfully achieved. The proposed system is flexible and scalable. For different classification applications, it can be modified easily according to number of inputs and number of reference data.