FPGA-based System for Real-Time Video Texture Analysis
Journal of Signal Processing Systems
Design of a real-time face detection parallel architecture using high-level synthesis
EURASIP Journal on Embedded Systems - Special issue on design and architectures for signal and image processing
Development of Real-Time Face Detection Architecture for Household Robot Applications
UAHCI '09 Proceedings of the 5th International on ConferenceUniversal Access in Human-Computer Interaction. Part II: Intelligent and Ubiquitous Interaction Environments
Fast and robust face detection on a parallel optimized architecture implemented on FPGA
IEEE Transactions on Circuits and Systems for Video Technology
Learning from 1,000,000 user-uploaded faces
ICME'09 Proceedings of the 2009 IEEE international conference on Multimedia and Expo
Digital Signal Processing
Real-time face detection using illumination invariant features
SCIA'07 Proceedings of the 15th Scandinavian conference on Image analysis
Video security algorithm aiming at the need of privacy protection
FSKD'09 Proceedings of the 6th international conference on Fuzzy systems and knowledge discovery - Volume 5
Boolean derivatives with application to edge detection for imaging systems
IEEE Transactions on Systems, Man, and Cybernetics, Part B: Cybernetics
Evolutionary-rough feature selection for face recognition
Transactions on rough sets XII
Correlation based speech-video synchronization
Pattern Recognition Letters
Digital Signal Processing
Design and VLSI implementation of a high-performance face detection engine
Computers and Electrical Engineering
Engineering Applications of Artificial Intelligence
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This paper proposes a new technique for face detection and lip feature extraction. A real-time field-programmable gate array (FPGA) implementation of the two proposed techniques is also presented. Face detection is based on a naive Bayes classifier that classifies an edge-extracted representation of an image. Using edge representation significantly reduces the model's size to only 5184 B, which is 2417 times smaller than a comparable statistical modeling technique, while achieving an 86.6% correct detection rate under various lighting conditions. Lip feature extraction uses the contrast around the lip contour to extract the height and width of the mouth, metrics that are useful for speech filtering. The proposed FPGA system occupies only 15 050 logic cells, or about six times less than a current comparable FPGA face detection system