A decision-theoretic generalization of on-line learning and an application to boosting
Journal of Computer and System Sciences - Special issue: 26th annual ACM symposium on the theory of computing & STOC'94, May 23–25, 1994, and second annual Europe an conference on computational learning theory (EuroCOLT'95), March 13–15, 1995
Detecting Faces in Images: A Survey
IEEE Transactions on Pattern Analysis and Machine Intelligence
Biometrics: Identity Verification in a Networked World
Biometrics: Identity Verification in a Networked World
Robust Real-Time Face Detection
International Journal of Computer Vision
A Parallel Architecture for Hardware Face Detection
ISVLSI '06 Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
Hybrid architectures for efficient and secure face authentication in embedded systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast and robust face detection on a parallel optimized architecture implemented on FPGA
IEEE Transactions on Circuits and Systems for Video Technology
Face detection using binary template matching and SVM
PRICAI'06 Proceedings of the 9th Pacific Rim international conference on Artificial intelligence
Face detection with the modified census transform
FGR' 04 Proceedings of the Sixth IEEE international conference on Automatic face and gesture recognition
Face detection using particle swarm optimization and support vector machines
SETN'10 Proceedings of the 6th Hellenic conference on Artificial Intelligence: theories, models and applications
Real-time face detection and lip feature extraction using field-programmable gate arrays
IEEE Transactions on Systems, Man, and Cybernetics, Part B: Cybernetics
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This paper proposes a novel hardware structure and field-programmable gate array (FPGA) implementation method for real-time detection of multiple human faces with robustness against illumination variations. These are designed to greatly improve face detection in various environments with using MCT techniques and the AdaBoost learning algorithm which is robust against variable illumination. We have designed, implemented, and verified the hardware architecture of the face detection engine for high-performance face detection and real-time processing. The face detection chip is developed by verifying and implementing it using a FPGA and an application-specific integrated circuit (ASIC). To verify and implement the chip, we used a Virtex5 LX330 FPGA board and a 0.18@mm 1-poly and 6-metal CMOS logic process. Performance results of the implementation and verification showed it is possible to detect at least 32 faces of a wide variety of sizes at a maximum speed of 147 frames per second.