Neural Network-Based Face Detection
IEEE Transactions on Pattern Analysis and Machine Intelligence
Detecting Faces in Images: A Survey
IEEE Transactions on Pattern Analysis and Machine Intelligence
Video compression with parallel processing
Parallel Computing - Parallel computing in image and video processing
Embedded Hardware Face Detection
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
A Real-Time Multi Face Detection Technique Using Positive-Negative Lines-of-Face Template
ICPR '04 Proceedings of the Pattern Recognition, 17th International Conference on (ICPR'04) Volume 1 - Volume 01
Convolutional Face Finder: A Neural Architecture for Fast and Robust Face Detection
IEEE Transactions on Pattern Analysis and Machine Intelligence
An architectural level design methodology for embedded face detection
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A Parallel Architecture for Hardware Face Detection
ISVLSI '06 Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
EURASIP Journal on Applied Signal Processing
Real-time face detection and lip feature extraction using field-programmable gate arrays
IEEE Transactions on Systems, Man, and Cybernetics, Part B: Cybernetics
Platform-based design from parallel C specifications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Performance of software-based MPEG-2 video encoder on parallel and distributed systems
IEEE Transactions on Circuits and Systems for Video Technology
Square patch feature based face detection architecture for high resolution smart camera
Proceedings of the Fourth ACM/IEEE International Conference on Distributed Smart Cameras
Facing the Multicore-Challenge II
Design and VLSI implementation of a high-performance face detection engine
Computers and Electrical Engineering
A hardware architecture for real-time object detection using depth and edge information
ACM Transactions on Embedded Computing Systems (TECS)
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In this paper, we present a parallel architecture for fast and robust face detection implemented on FPGA hardware. We propose the first implementation that meets both real-time requirements in an embedded context and face detection robustness within complex backgrounds. The chosen face detection method is the Convolutional Face Finder (CFF) algorithm, which consists of a pipeline of convolution and subsampling operations, followed by a multilayer perceptron. We present the design methodology of our face detection processor element (PE). This methodology was followed in order to optimize our implementation in terms of memory usage and parallelization efficiency. We then built a parallel architecture composed of a PE ring and an FIFO memory, resulting in a scalable system capable of processing images of different sizes. A ring of 25 PEs running at 80 MHz is able to process 127 QVGA images per second and performing real-time face detection on VGA images (35 images per second).