Design of a real-time face detection parallel architecture using high-level synthesis
EURASIP Journal on Embedded Systems - Special issue on design and architectures for signal and image processing
Fast and robust face detection on a parallel optimized architecture implemented on FPGA
IEEE Transactions on Circuits and Systems for Video Technology
A semi-supervised support vector machine based algorithm for face recognition
SMC'09 Proceedings of the 2009 IEEE international conference on Systems, Man and Cybernetics
EURASIP Journal on Advances in Signal Processing
AdaBoost-based face detection for embedded systems
Computer Vision and Image Understanding
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This paper describes a real-time multi face detection technique for color video sequences. A 3D rational skin color model and a positive-negative lines-of-face template are proposed to improve signal to noise ratio (SNR) in face detection. Steady State Genetic Algorithm (SSGA) is employed for lines-of-face detection from entire image. Hardware architecture is optimized for high-speed operation and small hardware resources. An experimental system is developed in Field Programmable Gate Array (FPGA), with only 40k gates for logic and 240k gates for memory. It detects 6 faces in real-time (30fps:every 33ms) from 320x240pixels (QVGA) color video sequences. Detection rate of 98% is achieved for 89 images including 205 faces from daily scenes.