Static scheduling of synchronous data flow programs for digital signal processing
IEEE Transactions on Computers
Determining the Order of Processor Transactions in StaticallyScheduled Multiprocessors
Journal of VLSI Signal Processing Systems
Detecting Faces in Images: A Survey
IEEE Transactions on Pattern Analysis and Machine Intelligence
Embedded Multiprocessors: Scheduling and Synchronization
Embedded Multiprocessors: Scheduling and Synchronization
Profiling tools for hardware/software partitioning of embedded applications
Proceedings of the 2003 ACM SIGPLAN conference on Language, compiler, and tool for embedded systems
Embedded Hardware Face Detection
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Faster maximum and minimum mean cycle algorithms for system-performance analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal edge-based shape detection
IEEE Transactions on Image Processing
Efficient computation of buffer capacities for multi-rate real-time systems with back-pressure
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Design of a real-time face detection parallel architecture using high-level synthesis
EURASIP Journal on Embedded Systems - Special issue on design and architectures for signal and image processing
Fast and robust face detection on a parallel optimized architecture implemented on FPGA
IEEE Transactions on Circuits and Systems for Video Technology
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Face detection and recognition research has attracted great attention in recent years. Automatic face detection has great potential in a large array of application areas, including banking and security system access control, video surveillance, and multimedia information retrieval. In this paper, we discuss an architectural level design methodology for implementation of an embedded face detection system on a reconfigurable system on chip. We present models for performance estimation and validate these models with experimental values obtained from implementing our system on an FPGA platform. This modeling approach is shown to be efficient, accurate, and intuitive for designers to work with. Using this approach, we present several design options that trade-off various architectural features.