Introductory Techniques for 3-D Computer Vision
Introductory Techniques for 3-D Computer Vision
A Tutorial on Support Vector Machines for Pattern Recognition
Data Mining and Knowledge Discovery
Real-Time Face Detection on a Configurable Hardware System
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Training Support Vector Machines: an Application to Face Detection
CVPR '97 Proceedings of the 1997 Conference on Computer Vision and Pattern Recognition (CVPR '97)
Integrated Person Tracking Using Stereo, Color, and Pattern Detection
CVPR '98 Proceedings of the IEEE Computer Society Conference on Computer Vision and Pattern Recognition
Robust Real-Time Face Detection
International Journal of Computer Vision
Convolutional Face Finder: A Neural Architecture for Fast and Robust Face Detection
IEEE Transactions on Pattern Analysis and Machine Intelligence
Evaluation of Features Detectors and Descriptors Based on 3D Objects
ICCV '05 Proceedings of the Tenth IEEE International Conference on Computer Vision (ICCV'05) Volume 1 - Volume 01
Accelerating Face Detection by Using Depth Information
PSIVT '09 Proceedings of the 3rd Pacific Rim Symposium on Advances in Image and Video Technology
Fpga-based face detection system using Haar classifiers
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Partially parallel architecture for AdaBoost-based detection with Haar-like features
IEEE Transactions on Circuits and Systems for Video Technology
Fast and robust face detection on a parallel optimized architecture implemented on FPGA
IEEE Transactions on Circuits and Systems for Video Technology
FPGA Implementation of Support Vector Machines for 3D Object Identification
ICANN '09 Proceedings of the 19th International Conference on Artificial Neural Networks: Part I
Fast point feature histograms (FPFH) for 3D registration
ICRA'09 Proceedings of the 2009 IEEE international conference on Robotics and Automation
A novel SoC architecture on FPGA for ultra fast face detection
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
A Hardware/Software Co-design of a Face Detection Algorithm Based on FPGA
ICMTMA '10 Proceedings of the 2010 International Conference on Measuring Technology and Mechatronics Automation - Volume 01
Towards hardware stereoscopic 3D reconstruction: a real-time FPGA computation of the disparity map
Proceedings of the Conference on Design, Automation and Test in Europe
FPGA-Accelerated Object Detection Using Edge Information
FPL '11 Proceedings of the 2011 21st International Conference on Field Programmable Logic and Applications
A Parallel Hardware Architecture for Real-Time Object Detection with Support Vector Machines
IEEE Transactions on Computers
A Flexible Parallel Hardware Architecture for AdaBoost-Based Real-Time Object Detection
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Edge-Directed Hardware Architecture for Real-Time Disparity Map Computation
IEEE Transactions on Computers
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Emerging embedded 3D vision systems for robotics and security applications utilize object detection to perform video analysis in order to intelligently interact with their host environment and take appropriate actions. Such systems have high performance and high detection-accuracy demands, while requiring low energy consumption, especially when dealing with embedded mobile systems. However, there is a large image search space involved in object detection, primarily because of the different sizes in which an object may appear, which makes it difficult to meet these demands. Hence, it is possible to meet such constraints by reducing the search space involved in object detection. To this end, this article proposes a depth and edge accelerated search method and a dedicated hardware architecture that implements it to provide an efficient platform for generic real-time object detection. The hardware integration of depth and edge processing mechanisms, with a support vector machine classification core onto an FPGA platform, results in significant speed-ups and improved detection accuracy. The proposed architecture was evaluated using images of various sizes, with results indicating that the proposed architecture is capable of achieving real-time frame rates for a variety of image sizes (271 fps for 320 × 240, 42 fps for 640 × 480, and 23 fps for 800 × 600) compared to existing works, while reducing the false-positive rate by 52%.