Towards hardware stereoscopic 3D reconstruction: a real-time FPGA computation of the disparity map

  • Authors:
  • S. Hadjitheophanous;C. Ttofis;A. S. Georghiades;T. Theocharides

  • Affiliations:
  • University of Cyprus, Nicosia, Cyprus;University of Cyprus, Nicosia, Cyprus;University of Cyprus, Nicosia, Cyprus;University of Cyprus, Nicosia, Cyprus

  • Venue:
  • Proceedings of the Conference on Design, Automation and Test in Europe
  • Year:
  • 2010

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Abstract

Stereoscopic 3D reconstruction is an important algorithm in the field of Computer Vision, with a variety of applications in embedded and real-time systems. Existing software-based implementations cannot satisfy the performance requirements for such constrained systems; hence an embedded hardware mechanism might be more suitable. In this paper, we present an architecture of a 3D reconstruction system for stereoscopic images, which we implement on Virtex2 Pro FPGA. The architecture uses a Sobel edge detector to achieve real-time (75 fps) performance, and is configurable in terms of various application parameters, making it suitable for a number of application environments. The paper also presents a design exploration on algorithmic parameters such as disparity range, correlation window size, and input image size, illustrating the impact on the performance for each parameter.