Multiple Stereo Matching Using an Extended Architecture

Authors:
Miguel Arias-Estrada;Juan M. Xicotencatl
Affiliations:
-;-
Venue:
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Year:
2001

Citing 2
Cited 3

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Towards hardware stereoscopic 3D reconstruction: a real-time FPGA computation of the disparity map

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Hardware design considerations for edge-accelerated stereo correspondence algorithms

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Towards accurate hardware stereo correspondence: a real-time FPGA implementation of a segmentation-based adaptive support weight algorithm

DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe

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Abstract

In this paper, an FPGA based architecture for stereo vision is presented. The architecture provides a high-density disparity map in real time. The architecture is based on area comparison between an image pair using the sum of absolute differences. The architecture scans the input images in partial columns, which are then processed in parallel. The system performs monolithically on a pair of images in real time. An extension to the basic architecture is proposed in order to compute disparity maps on more than 2 images.