ACM Computing Surveys (CSUR)
Maximum-Likelihood Image Matching
IEEE Transactions on Pattern Analysis and Machine Intelligence
A Taxonomy and Evaluation of Dense Two-Frame Stereo Correspondence Algorithms
International Journal of Computer Vision
Maximum Likelihood Stereo Matching
ICPR '00 Proceedings of the International Conference on Pattern Recognition - Volume 1
Advances in Computational Stereo
IEEE Transactions on Pattern Analysis and Machine Intelligence
Robustness to Noise of Stereo Matching
ICIAP '03 Proceedings of the 12th International Conference on Image Analysis and Processing
Computational Experiments with a Feature Based Stereo Algorithm
IEEE Transactions on Pattern Analysis and Machine Intelligence
Flexible hardware-based stereo matching
EURASIP Journal on Embedded Systems - Special issue on design and architectures for signal and image processing
FPGA based disparity map computation with vergence control
Microprocessors & Microsystems
Computer Vision and Image Understanding
Towards hardware stereoscopic 3D reconstruction: a real-time FPGA computation of the disparity map
Proceedings of the Conference on Design, Automation and Test in Europe
Design and hardware implementation of a stereo-matching system based on dynamic programming
Microprocessors & Microsystems
Hardware design considerations for edge-accelerated stereo correspondence algorithms
VLSI Design - Special issue on VLSI Circuits, Systems, and Architectures for Advanced Image and Video Compression Standards
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Real-time three-dimensional vision would support various applications including a passive system for collision avoidance. It is a good alternative of active systems, which are subject to interference in noisy environments. In this paper, we investigate the optimization of real-time stereo vision with respect to resource usage. Correlation techniques using a simple sum of absolute differences(SAD) is popular having good performance. However, processing even a small image takes seconds. In order to provide depth maps at frame rate around 30fps, which typical cameras can provide, hardware accelerations are necessary. Regular structures, linear data flow and abundant parallelism make the correlation algorithm a good candidate for reconfigurable hardware. We implemented versions of SAD algorithms in VHDL and synthesized them to determine resource requirements and performance. By decomposing a SAD correlator into column SAD calculator and row SAD calculator with buffers in between we showed around 50% savings in resource usage. By altering the shape of correlation windows we found that a ‘short and wide' rectangular window reduced storage requirements without sacrificing quality compared to a square one.