Determining the Epipolar Geometry and its Uncertainty: A Review
International Journal of Computer Vision
A Taxonomy and Evaluation of Dense Two-Frame Stereo Correspondence Algorithms
International Journal of Computer Vision
A Stereo Matching Algorithm with an Adaptive Window: Theory and Experiment
IEEE Transactions on Pattern Analysis and Machine Intelligence
Non-parametric Local Transforms for Computing Visual Correspondence
ECCV '94 Proceedings of the Third European Conference-Volume II on Computer Vision - Volume II
CAMP '00 Proceedings of the Fifth IEEE International Workshop on Computer Architectures for Machine Perception (CAMP'00)
Real-time stereo vision on the PARTS reconfigurable computer
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Color Stereo Vision Using Hierarchical Block Matching and Active Color Illumination
ICPR '96 Proceedings of the 1996 International Conference on Pattern Recognition (ICPR '96) Volume I - Volume 7270
Advances in Computational Stereo
IEEE Transactions on Pattern Analysis and Machine Intelligence
Tyzx DeepSea High Speed Stereo Vision System
CVPRW '04 Proceedings of the 2004 Conference on Computer Vision and Pattern Recognition Workshop (CVPRW'04) Volume 3 - Volume 03
On the Computational Power of Winner-Take-All
Neural Computation
The Tyzx DeepSea G2 Vision System, ATaskable, Embedded Stereo Camera
CVPRW '06 Proceedings of the 2006 Conference on Computer Vision and Pattern Recognition Workshop
International Journal of Computer Vision
VoC: a reconfigurable matrix for stereo vision processing
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
High-accuracy stereo depth maps using structured light
CVPR'03 Proceedings of the 2003 IEEE computer society conference on Computer vision and pattern recognition
Comparison of nonparametric transformations and bit vector matching for stereo correlation
IWCIA'04 Proceedings of the 10th international conference on Combinatorial Image Analysis
Real-time stereo vision on a reconfigurable system
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Reliability analysis of the rank transform for stereo matching
IEEE Transactions on Systems, Man, and Cybernetics, Part B: Cybernetics
Measuring the Gap Between FPGAs and ASICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
FPGA based disparity map computation with vergence control
Microprocessors & Microsystems
Accurate hardware-based stereo vision
Computer Vision and Image Understanding
Robotic mapping and localization with real-time dense stereo on reconfigurable hardware
International Journal of Reconfigurable Computing - Special issue on selected papers from ReconFig 2009 International conference on reconfigurable computing and FPGAs (ReconFig 2009)
Design and hardware implementation of a stereo-matching system based on dynamic programming
Microprocessors & Microsystems
A real-time fuzzy hardware structure for disparity map computation
Journal of Real-Time Image Processing
A reconfigurable disparity engine for stereovision in advanced driver assistance systems
ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
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To enable adaptive stereo vision for hardware-based embedded stereo vision systems, we propose a novel technique for implementing a flexible block size, disparity range, and frame rate. By reusing existing resources of a static architecture, rather than dynamic reconfiguration, our technique is compatible with application specific integrated circuit (ASIC) as well as field programmable gate array (FPGA) implementations. We present the corresponding block diagrams and their implementation in our hardware-based stereo matching architecture. Furthermore, we show the impact of flexible stereo matching on the generated disparity maps for the sum of absolute differences (SADs), rank, and census transform algorithms. Finally, we discuss the resource usage and achievable performance when synthesized for an Altera Stratix II FPGA.