Using chromatic information in edge-based stereo correspondence
CVGIP: Image Understanding
Three-dimensional computer vision: a geometric viewpoint
Three-dimensional computer vision: a geometric viewpoint
Defuzzification: criteria and classification
Fuzzy Sets and Systems
Using Real-Time Stereo Vision for Mobile Robot Navigation
Autonomous Robots
Calculating Dense Disparity Maps from Color Stereo Images, an Efficient Implementation
International Journal of Computer Vision
Dense Features for Semi-Dense Stereo Correspondence
International Journal of Computer Vision
Real-time stereo vision on the PARTS reconfigurable computer
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Improvements in Real-Time Correlation-Based Stereo Vision
SMBV '01 Proceedings of the IEEE Workshop on Stereo and Multi-Baseline Vision (SMBV'01)
Fast Unambiguous Stereo Matching Using Reliability-Based Dynamic Programming
IEEE Transactions on Pattern Analysis and Machine Intelligence
Near Real-Time Reliable Stereo Matching Using Programmable Graphics Hardware
CVPR '05 Proceedings of the 2005 IEEE Computer Society Conference on Computer Vision and Pattern Recognition (CVPR'05) - Volume 1 - Volume 01
A Dense Stereo Matching Using Two-Pass Dynamic Programming with Generalized Ground Control Points
CVPR '05 Proceedings of the 2005 IEEE Computer Society Conference on Computer Vision and Pattern Recognition (CVPR'05) - Volume 2 - Volume 02
Reconfigurable hardware implementation of a phase-correlation stereoalgorithm
Machine Vision and Applications
FPGA implementation of a nonlinear two dimensional fuzzy filter
ICASSP '99 Proceedings of the Acoustics, Speech, and Signal Processing, 1999. on 1999 IEEE International Conference - Volume 04
Editorial: field-programmable gate arrays in embedded systems
EURASIP Journal on Embedded Systems
Real-time disparity map computation module
Microprocessors & Microsystems
Flexible hardware-based stereo matching
EURASIP Journal on Embedded Systems - Special issue on design and architectures for signal and image processing
Video-rate stereo depth measurement on programmable hardware
CVPR'03 Proceedings of the 2003 IEEE computer society conference on Computer vision and pattern recognition
Extracting dense features for visual correspondence with graph cuts
CVPR'03 Proceedings of the 2003 IEEE computer society conference on Computer vision and pattern recognition
IEEE Transactions on Pattern Analysis and Machine Intelligence
Consequences of the digitization on the performance of a fuzzy logic controller
IEEE Transactions on Fuzzy Systems
Noise reduction by fuzzy image filtering
IEEE Transactions on Fuzzy Systems
GOLD: a parallel real-time stereo vision system for generic obstacle and lane detection
IEEE Transactions on Image Processing
Real-Time Stereo Matching Using Orthogonal Reliability-Based Dynamic Programming
IEEE Transactions on Image Processing
FPGA-based real-time optical-flow system
IEEE Transactions on Circuits and Systems for Video Technology
A Real-Time Occlusion Aware Hardware Structure for Disparity Map Computation
ICIAP '09 Proceedings of the 15th International Conference on Image Analysis and Processing
Low-cost FPGA stereo vision system for real time disparity maps calculation
Microprocessors & Microsystems
Real-time architecture for a robust multi-scale stereo engine on FPGA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast implementation of dense stereo vision algorithms on a highly parallel SIMD architecture
Journal of Real-Time Image Processing
Efficient and high performance FPGA-based rectification architecture for stereo vision
Microprocessors & Microsystems
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Stereo images acquired by a stereo camera setup provide depth estimation of a scene. Numerous machine vision applications deal with retrieval of 3D information. Disparity map recovery from a stereo image pair involves computationally complex algorithms. Previous methods of disparity map computation are mainly restricted to software-based techniques on general-purpose architectures, presenting relatively high execution time. In this paper, a new hardware-implemented real-time disparity map computation module is realized. This enables a hardware-based fuzzy inference system parallel-pipelined design, for the overall module, implemented on a single FPGA device with a typical operating frequency of 138 MHz. This provides accurate disparity map computation at a rate of nearly 440 frames per second, given a stereo image pair with a disparity range of 80 pixels and 640 脳 480 pixels spatial resolution. The proposed method allows a fast disparity map computational module to be built, enabling a suitable module for real-time stereo vision applications.