A Taxonomy and Evaluation of Dense Two-Frame Stereo Correspondence Algorithms
International Journal of Computer Vision
Real-Time Correlation-Based Stereo Vision with Reduced Border Errors
International Journal of Computer Vision
A Miniature Stereo Vision Machine (MSVM-III) for Dense Disparity Mapping
ICPR '04 Proceedings of the Pattern Recognition, 17th International Conference on (ICPR'04) Volume 1 - Volume 01
Tyzx DeepSea High Speed Stereo Vision System
CVPRW '04 Proceedings of the 2004 Conference on Computer Vision and Pattern Recognition Workshop (CVPRW'04) Volume 3 - Volume 03
A PC-based real-time stereo vision system
Machine Graphics & Vision International Journal
A versatile stereo implementation on commodity graphics hardware
Real-Time Imaging
Real-Time Parallel Implementation of SSD Stereo Vision Algorithm on CSX SIMD Architecture
ISVC '09 Proceedings of the 5th International Symposium on Advances in Visual Computing: Part I
Highly parallel implementation of Harris Corner detector on CSX SIMD architecture
Euro-Par 2010 Proceedings of the 2010 conference on Parallel processing
Image processing applications on a low power highly parallel SIMD architecture
AERO '11 Proceedings of the 2011 IEEE Aerospace Conference
A real-time fuzzy hardware structure for disparity map computation
Journal of Real-Time Image Processing
Real-time dense stereo for intelligent vehicles
IEEE Transactions on Intelligent Transportation Systems
Real-time disparity map computation using the cell broadband engine
Journal of Real-Time Image Processing
Comparison of dense stereo using CUDA
ECCV'10 Proceedings of the 11th European conference on Trends and Topics in Computer Vision - Volume Part II
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In this paper, we present faster than real-time implementation of a class of dense stereo vision algorithms on a low-power massively parallel SIMD architecture, the CSX700. With two cores, each with 96 Processing Elements, this SIMD architecture provides a peak computation power of 96 GFLOPS while consuming only 9 Watts, making it an excellent candidate for embedded computing applications. Exploiting full features of this architecture, we have developed schemes for an efficient parallel implementation with minimum of overhead. For the sum of squared differences (SSD) algorithm and for VGA (640 脳 480) images with disparity ranges of 16 and 32, we achieve a performance of 179 and 94 frames per second (fps), respectively. For the HDTV (1,280 脳 720) images with disparity ranges of 16 and 32, we achieve a performance of 67 and 35 fps, respectively. We have also implemented more accurate, and hence more computationally expensive variants of the SSD, and for most cases, particularly for VGA images, we have achieved faster than real-time performance. Our results clearly demonstrate that, by developing careful parallelization schemes, the CSX architecture can provide excellent performance and flexibility for various embedded vision applications.