Highly parallel implementation of Harris Corner detector on CSX SIMD architecture

Authors:
Fouzhan Hosseini;Amir Fijany;Jean-Guy Fontaine
Affiliations:
Italian Institute of Technology, Genova, Italy;Italian Institute of Technology, Genova, Italy;Italian Institute of Technology, Genova, Italy
Venue:
Euro-Par 2010 Proceedings of the 2010 conference on Parallel processing
Year:
2010

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Abstract

We present a much faster than real-time implementation of Harris Corner Detector (HCD) on a low-power, highly parallel, SIMD architecture, the ClearSpeed CSX700, with application for mobile robots and humanoids. HCD is a popular feature detector due to its invariance to rotation, scale, illumination variation and image noises. We have developed strategies for efficient parallel implementation of HCD on CSX700, and achieved a performance of 465 frames per second (fps) for images of 640×480 resolution and 142 fps for 1280×720 resolution. For a typical real-time application with 30 fps, our fast implementation represents a very small fraction (less than %10) of available time for each frame and thus allowing enough time for performing other computations. Our results indicate that the CSX architecture is indeed a good candidate for achieving low-power supercomputing capability, as well as flexibility.