A Taxonomy and Evaluation of Dense Two-Frame Stereo Correspondence Algorithms
International Journal of Computer Vision
Real-Time Correlation-Based Stereo Vision with Reduced Border Errors
International Journal of Computer Vision
Real-time stereo vision on the PARTS reconfigurable computer
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
A versatile stereo implementation on commodity graphics hardware
Real-Time Imaging
High-Quality Real-Time Stereo Using Adaptive Cost Aggregation and Dynamic Programming
3DPVT '06 Proceedings of the Third International Symposium on 3D Data Processing, Visualization, and Transmission (3DPVT'06)
Low-Cost Stereo Vision on an FPGA
FCCM '07 Proceedings of the 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Highly parallel implementation of Harris Corner detector on CSX SIMD architecture
Euro-Par 2010 Proceedings of the 2010 conference on Parallel processing
Fast implementation of dense stereo vision algorithms on a highly parallel SIMD architecture
Journal of Real-Time Image Processing
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We present a faster than real-time parallel implementation of standard sum of squared differences (SSD) stereo vision algorithm, on an SIMD architecture, the CSX700. To our knowledge, this is the first highly parallel implementation of this algorithm using 192 processing elements. For disparity range of 16 pixels, we have achieved the rate of 160 and 59 stereo pairs per second on 640x480 and 1280x720 images, respectively. Since this implementation is much faster than real time, it leaves enough time for performing other machine vision applications in real time. Our results demonstrate that CSX architecture is a powerful processor for (low level) computer vision applications. Due to the low-power consumption of CSX architecture, it can be a good candidate for mobile computer vision applications.