Techniques for disparity measurement
CVGIP: Image Understanding
Real-time vergence control for binocular robots
International Journal of Computer Vision
Three-dimensional computer vision: a geometric viewpoint
Three-dimensional computer vision: a geometric viewpoint
An intensity-based, coarse-to-fine approach to reliably measure binocular disparity
CVGIP: Image Understanding
Machine vision
Hierarchical stereo and motion correspondence using feature groupings
International Journal of Computer Vision
Dynamic Vergence Using Log-Polar Images
International Journal of Computer Vision
Using Real-Time Stereo Vision for Mobile Robot Navigation
Autonomous Robots
A Taxonomy and Evaluation of Dense Two-Frame Stereo Correspondence Algorithms
International Journal of Computer Vision
A Stereo Machine for Video-Rate Dense Depth Mapping and Its New Applications
CVPR '96 Proceedings of the 1996 Conference on Computer Vision and Pattern Recognition (CVPR '96)
Real-time stereo vision on the PARTS reconfigurable computer
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Towards an active visual observer
ICCV '95 Proceedings of the Fifth International Conference on Computer Vision
Advances in Computational Stereo
IEEE Transactions on Pattern Analysis and Machine Intelligence
Near Real-Time Reliable Stereo Matching Using Programmable Graphics Hardware
CVPR '05 Proceedings of the 2005 IEEE Computer Society Conference on Computer Vision and Pattern Recognition (CVPR'05) - Volume 1 - Volume 01
A Real-Time Large Disparity Range Stereo-System using FPGAs
ICVS '06 Proceedings of the Fourth IEEE International Conference on Computer Vision Systems
Reconfigurable hardware implementation of a phase-correlation stereoalgorithm
Machine Vision and Applications
An Algorithm for Adaptive Mean Filtering and Its Hardware Implementation
Journal of VLSI Signal Processing Systems
Real-time disparity map computation module
Microprocessors & Microsystems
A New Miniaturized Embedded Stereo-Vision System (MESVS-I)
CRV '08 Proceedings of the 2008 Canadian Conference on Computer and Robot Vision
Flexible hardware-based stereo matching
EURASIP Journal on Embedded Systems - Special issue on design and architectures for signal and image processing
IEEE Transactions on Pattern Analysis and Machine Intelligence
High speed computation of the optical flow
ICIAP'05 Proceedings of the 13th international conference on Image Analysis and Processing
Real-time stereo vision on a reconfigurable system
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
FPGA-based real-time optical-flow system
IEEE Transactions on Circuits and Systems for Video Technology
Efficient and high performance FPGA-based rectification architecture for stereo vision
Microprocessors & Microsystems
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Depth estimation in a scene using image pairs acquired by a stereo camera setup, is one of the important tasks of stereo vision systems. The disparity between the stereo images allows for 3D information acquisition which is indispensable in many machine vision applications. Practical stereo vision systems involve wide ranges of disparity levels. Considering that disparity map extraction of an image is a computationally demanding task, practical real-time FPGA based algorithms require increased device utilization resource usage, depending on the disparity levels operational range, which leads to significant power consumption. In this paper a new hardware-efficient real-time disparity map computation module is developed. The module constantly estimates the precisely required range of disparity levels upon a given stereo image set, maintaining this range as low as possible by verging the stereo setup cameras axes. This enables a parallel-pipelined design, for the overall module, realized on a single FPGA device of the Altera Stratix IV family. Accurate disparity maps are computed at a rate of more than 320 frames per second, for a stereo image pair of 640x480 pixels spatial resolution with a disparity range of 80 pixels. The presented technique provides very good processing speed at the expense of accuracy, with very good scalability in terms of disparity levels. The proposed method enables a suitable module delivering high performance in real-time stereo vision applications, where space and power are significant concerns.