Static scheduling of synchronous data flow programs for digital signal processing
IEEE Transactions on Computers
The program dependence graph and its use in optimization
ACM Transactions on Programming Languages and Systems (TOPLAS)
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
Register allocation via hierarchical graph coloring
PLDI '91 Proceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation
DISC: dynamic instruction stream computer
MICRO 24 Proceedings of the 24th annual international symposium on Microarchitecture
Enhanced region scheduling on a program dependence graph
MICRO 25 Proceedings of the 25th annual international symposium on Microarchitecture
The ESTEREL synchronous programming language: design, semantics, implementation
Science of Computer Programming
Register relocation: flexible contexts for multithreading
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
Multiple threads in cyclic register windows
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
Hardware and software for functional and fine grain parallelism
Hardware and software for functional and fine grain parallelism
The effectiveness of multiple hardware contexts
ASPLOS VI Proceedings of the sixth international conference on Architectural support for programming languages and operating systems
Implementation of the data-flow synchronous language SIGNAL
PLDI '95 Proceedings of the ACM SIGPLAN 1995 conference on Programming language design and implementation
Recent developments in high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Efficient compilation of process-based concurrent programs without run-time scheduling
Proceedings of the conference on Design, automation and test in Europe
Efficient scheduling of conditional behaviors for high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Hardware-Software Cosynthesis for Digital Systems
IEEE Design & Test
A PDG-based Tool and its Use in Analyzing Program Control Dependences
PACT '94 Proceedings of the IFIP WG10.3 Working Conference on Parallel Architectures and Compilation Techniques
Register allocation & spilling via graph coloring
SIGPLAN '82 Proceedings of the 1982 SIGPLAN symposium on Compiler construction
Techniques for Software Thread Integration in Real-Time Embedded Systems
RTSS '98 Proceedings of the IEEE Real-Time Systems Symposium
System-Level Issues for Software Thread Integration: Guest Triggering and Host Selection
RTSS '99 Proceedings of the 20th IEEE Real-Time Systems Symposium
Compiling for Fine-Grain Concurrency: Planning and Performing Software Thread Integration
RTSS '02 Proceedings of the 23rd IEEE Real-Time Systems Symposium
SPARK: A High-Lev l Synthesis Framework For Applying Parallelizing Compiler Transformations
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Software thread integration for hardware to software migration
Software thread integration for hardware to software migration
Hardware to Software Migration with Real-Time Thread Integration
EUROMICRO '98 Proceedings of the 24th Conference on EUROMICRO - Volume 1
Extending STI for demanding hard-real-time systems
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
An Esterel compiler for large control-dominated systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Using global code motions to improve the quality of results for high-level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Embedded systems require control of many concurrent real-time activities, leading to system designs that feature a variety of hardware peripherals, with each providing a specific, dedicated service. These peripherals increase system size, cost, weight, and design time. Software thread integration (STI) provides low-cost thread concurrency on general-purpose processors by automatically interleaving multiple threads of control into one. This simplifies hardware to software migration (which eliminates dedicated hardware) and can help embedded system designers meet design constraints, such as size, weight and cost. We have developed concepts for performing STI and have implemented many in our automated postpass compiler Thrint. Here we present the transformations and examine how well the compiler integrates threads for two display applications. We examine the integration procedure, the processor load, and code memory expansion. Integration allows reclamation of CPU idle time, allowing run-time speedups of 1.6x to 3.6x.