Efficient Storage Management for Temporary Values in Concurrent Programming Languages
IEEE Transactions on Computers
Operation systems: advanced concepts
Operation systems: advanced concepts
MASA: a multithreaded processor architecture for parallel symbolic computing
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
The portable common runtime approach to interoperability
SOSP '89 Proceedings of the twelfth ACM symposium on Operating systems principles
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
The interaction of architecture and operating system design
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
Flexible register management for sequential programs
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
Low-latency message communication support for the AP1000
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
APRIL: a processor architecture for multiprocessing
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
EDS: A Parallel Computer System for Advanced Information Processing
PARLE '92 Proceedings of the 4th International PARLE Conference on Parallel Architectures and Languages Europe
RISC I: A Reduced Instruction Set VLSI Computer
ISCA '81 Proceedings of the 8th annual symposium on Computer Architecture
Hardware-software trade-offs in a direct Rambus implementation of the RAMpage memory hierarchy
Proceedings of the eighth international conference on Architectural support for programming languages and operating systems
The Named-State Register File: Implementation and Performance
HPCA '95 Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture
Software thread integration for embedded system display applications
ACM Transactions on Embedded Computing Systems (TECS)
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Multi-threading is often used to compile logic and functional languages, and implement parallel C libraries. Fine-grain multi-threading requires rapid context switching, which can be slow on architectures with register windows. In past, researchers have either proposed new hardware support for dynamic allocation of windows to threads, or have sacrificed fast procedure calls by fixed allocation of windows to threads.In this paper, a novel window management algorithm, which retains both fast procedure calls and fast context switching, is proposed. The algorithm has been implemented on the SPARC processor by modifying window trap handlers. A quantitative evaluation of the scheme using a multi-threaded application with various concurrency and granularity levels is given. The evaluation shows that the proposed scheme always does better than the other schemes. Some implications for multi-threaded architectures are also presented.