Verification of datapath and controller generation phase in high-level synthesis of digital circuits

Authors:
Chandan Karfa;Dipankar Sarkar;Chittaranjan Mandal
Affiliations:
Department of Computer Science and Engineering, Indian Institute of Technology, Kharagpur, India;Department of Computer Science and Engineering, Indian Institute of Technology, Kharagpur, India;Department of Computer Science and Engineering, Indian Institute of Technology, Kharagpur, India
Venue:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Year:
2010

Citing 22
Cited 2

Some Inference Rules for Integer Arithmetic for Verification of Flowchart Programs on Integers

IEEE Transactions on Software Engineering
Control optimization in high-level synthesis using behavioral don't cares

DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
1995 high level synthesis design repository

ISSS '95 Proceedings of the 8th international symposium on System synthesis
Verification of RTL generated from scheduled behavior in a high-level synthesis flow

Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Automatic verification of scheduling results in high-level synthesis

DATE '99 Proceedings of the conference on Design, automation and test in Europe
Accounting for various register allocation schemes during post-synthesis verification of RTL designs

DATE '99 Proceedings of the conference on Design, automation and test in Europe
A compositional model for the functional verification of high-level synthesis results

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on the 11th international symposium on system-level synthesis and design (ISSS'98)
A Methodology for Automated Verification of Synthesized RTL Designs and Its Integration with a High-Level Synthesis Tool

FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
An approach to high-level synthesis system validation using formally verified transformations

HLDVT '00 Proceedings of the IEEE International High-Level Validation and Test Workshop (HLDVT'00)
Using Algebraic Transformations to Optimize Expression Evaluation in Scientific Code

PACT '98 Proceedings of the 1998 International Conference on Parallel Architectures and Compilation Techniques
SPARK: A High-Lev l Synthesis Framework For Applying Parallelizing Compiler Transformations

VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Theorem Proving Guided Development of Formal Assertions in a Resource-Constrained Scheduler for High-Level Synthesis

ICCD '98 Proceedings of the International Conference on Computer Design
Automated Formal Verification of Scheduling Process Using Finite State Machines with Datapath (FSMD)

ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
Equivalence checking between behavioral and RTL descriptions with virtual controllers and datapaths

ACM Transactions on Design Automation of Electronic Systems (TODAES)
Early cutpoint insertion for high-level software vs. RTL formal combinational equivalence verification

Proceedings of the 43rd annual Design Automation Conference
Verification method of dataflow algorithms in high-level synthesis

Journal of Systems and Software
Register Sharing Verification During Data-Path Synthesis

ICCTA '07 Proceedings of the International Conference on Computing: Theory and Applications
Verification of Data-path and Controller Generation Phase of High-level Synthesis

ADCOM '07 Proceedings of the 15th International Conference on Advanced Computing and Communications
Automated formal verification of scheduling with speculative code motions

Proceedings of the 18th ACM Great Lakes symposium on VLSI
Using global code motions to improve the quality of results for high-level synthesis

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An Equivalence-Checking Method for Scheduling Verification in High-Level Synthesis

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimizing power using transformations

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Formal verification of code motion techniques using data-flow-driven equivalence checking

ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
Experimentation with SMT solvers and theorem provers for verification of loop and arithmetic transformations

Proceedings of the 5th IBM Collaborative Academia Research Exchange Workshop

Quantified Score

Hi-index	0.03

Visualization

Abstract

A formal verification method of the datapath and controller generation phase of a high-level synthesis (HLS) process is described in this paper. The goal is achieved in two steps. In the first step, the datapath interconnection and the controller finite state machine description generated by a high-level synthesis process are analyzed to obtain the register transfer-operations executed in the datapath for a given control assertion pattern in each control step. In the second step, an equivalence checking method is deployed to establish equivalence between the input and the output behaviors of this phase. A rewriting method has been developed for the first step. Unlike many other reported techniques, our method is capable of validating pipelined and multicycle operations, if any, spanning over several states. The correctness and complexity of the presented method have been treated formally. The method is implemented and integrated with an existing HLS tool, called structured architecture synthesis tool. The experimental results on several HLS benchmarks indicate the effectiveness of the presented method.