Automatic verification of finite-state concurrent systems using temporal logic specifications
ACM Transactions on Programming Languages and Systems (TOPLAS)
REAL: a program for REgister ALlocation
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
A global, dynamic register allocation and binding for a data path synthesis system
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Symbolic model checking: an approach to the state explosion problem
Symbolic model checking: an approach to the state explosion problem
HAL: a multi-paradigm approach to automatic data path synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Synthesis of Digital Design from Recursive Equations
Synthesis of Digital Design from Recursive Equations
DSS: A Distributed High-Level Synthesis System
IEEE Design & Test
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Proceedings of the 11th International Conference on Theorem Proving in Higher Order Logics
Automated High-level Verification Against Clocked Algorithmic Specifications
CHDL '93 Proceedings of the 11th IFIP WG10.2 International Conference sponsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC on Computer Hardware Description Languages and their Applications
Facet: A procedure for the automated synthesis of digital systems
DAC '83 Proceedings of the 20th Design Automation Conference
ICCD '98 Proceedings of the International Conference on Computer Design
EURO-DAC '90 Proceedings of the conference on European design automation
Verification of datapath and controller generation phase in high-level synthesis of digital circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Formal verification of code motion techniques using data-flow-driven equivalence checking
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
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