Automatic verification of pipelined microprocessors
DAC '94 Proceedings of the 31st annual Design Automation Conference
An Automaton Model for Scheduling Constraints in Synchronous Machines
IEEE Transactions on Computers
Accounting for various register allocation schemes during post-synthesis verification of RTL designs
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Automated Correctness Condition Generation for Formal Verification ofSynthesized RTL Designs
Formal Methods in System Design - Special issue on formal methods for computer-added design
Multiway Decision Graphs for Automated Hardware Verification
Formal Methods in System Design
Automated Verification of Behavioral Equivalence for Microprocessors
IEEE Transactions on Computers
Hi-index | 0.01 |