Automated Correctness Condition Generation for Formal Verification ofSynthesized RTL Designs

  • Authors:

  • Nazanin Mansouri;Ranga Vemuri

  • Affiliations:

  • Digital Design Environments Laboratory, ECECS Department, University of Cincinnati, Cincinnati, Ohio 45221-0030, USA. nmansour@ececs.uc.edu;Digital Design Environments Laboratory, ECECS Department, University of Cincinnati, Cincinnati, Ohio 45221-0030, USA. ranga.vemuri@uc.edu

  • Venue:
  • Formal Methods in System Design - Special issue on formal methods for computer-added design
  • Year:
  • 2000

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Abstract

High-level synthesis tools generate register-transfer leveldesigns from algorithmic behavioral specifications. The high-levelsynthesis process typically consists of dependency graph scheduling,functional unit allocation, register allocation, interconnect allocationand controller generation tasks. Widely used algorithms for these tasksretain the overall control flow structure of the behavioralspecification allowing code motion only within basic blocks. Further,high-level synthesis algorithms are oblivious to the mathematicalproperties of arithmetic and logic operators. Selecting and sharingof RTL library modules are solely based on matching uninterpretedfunction symbolsand constants. Many researchers have noted that these features ofhigh-level synthesis algorithms canbe exploited to develop efficient verification strategies forsynthesized designs. This paper reports a verification techniquethat effectively exploits these features toachieve efficient and fully automated verification ofsynthesized designs and its incorporation in a high-level synthesis tool.In our technique, a correctness condition generator is tightlyintegrated with a high-level synthesis tool to automaticallygenerate (1) formal specifications of the behavior and the RTLdesign including the data path and the controller, (2) the correctnesslemmas establishing equivalence between the synthesizedRTL design and its behavioral specification, and (3) their proofscripts that can be submitted to a higher-order logic proof checkerwithout further human interaction. This approach is based on theidentification, by the synthesis tool during the synthesis process, ofthe binding between critical specification variables and criticalregisters in the RTL design, and between the critical states in thebehavior and the corresponding states in the RTL design.We have implemented our verification technique inconjunction with a relatively mature high-level synthesis tool. Wereport experimental results indicating the effectiveness of the proposedtechnique and summarize our ongoing work to further strengthen it.