High-level synthesis in an industrial environment
IBM Journal of Research and Development - Special issue: IBM CMOS technology
Behavioral synthesis methodology for HDL-based specification and validation
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Binary decision diagrams and beyond: enabling technologies for formal verification
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Simulation-Based Verification for High-Level Synthesis
IEEE Design & Test
Verification of RTL generated from scheduled behavior in a high-level synthesis flow
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Automated Correctness Condition Generation for Formal Verification ofSynthesized RTL Designs
Formal Methods in System Design - Special issue on formal methods for computer-added design
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Symbolic Checking of Signal-Transition Consistency for Verifying High-Level Designs
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
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Verifying equivalence of the behavioral specification and scheduled implementation is a significant problem in high-level synthesis, because scheduling changes the cycle-by-cycle behavior. The authors present a practical method for comparing simulation results for the two using the same vectors