Test program generation for functional verification of PowerPC processors in IBM
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
A study in coverage-driven test generation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Semi-formal test generation with genevieve
Proceedings of the 38th annual Design Automation Conference
Symbolic Model Checking
Observable Time Windows: Verifying High-Level Synthesis Results
IEEE Design & Test
Coverage-Directed Test Generation Using Symbolic Techniques
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
Observable Time Windows: Verifying the Results of High-Level Synthesis
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Functional Verification of DMA Controllers
Journal of Electronic Testing: Theory and Applications
Software-Based Testing for System Peripherals
Journal of Electronic Testing: Theory and Applications
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This document describes a successful application of a semi-formal test generation technique to the verification of Direct Memory Access Controller (DMAC) of ST50, a new general purpose RISC microprocessor developed by STMicroelectronics and Hitachi. Like other memory-related devices, the DMA controller challenges formal techniques because of the state explosion problem. To cope with the challenge, abstraction mechanism is applied during test generation: several abstract models are created in order to verify different functional aspects of the design. We also propose a practical solution to overcome a temporal abstraction problem that arises when tests issued from an abstract model have to be applied during real design simulation.