High-level synthesis in an industrial environment
IBM Journal of Research and Development - Special issue: IBM CMOS technology
Behavioral synthesis methodology for HDL-based specification and validation
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Binary decision diagrams and beyond: enabling technologies for formal verification
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Simulation-Based Verification for High-Level Synthesis
IEEE Design & Test
Verification by simulation comparison using interface synthesi
Proceedings of the conference on Design, automation and test in Europe
Extending the transaction level modeling approach for fast communication architecture exploration
Proceedings of the 41st annual Design Automation Conference
Fast exploration of bus-based on-chip communication architectures
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Fast exploration of bus-based communication architectures at the CCATB abstraction
ACM Transactions on Embedded Computing Systems (TECS)
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One of the main problems in high-level synthesis has been the lack of verification techniques for checking the equivalence between the behavioral specification and the scheduled implementation. Due to scheduling it may not be possible to compare simulation results before and after high-level synthesis using the same simulation drivers. Given that simulation is the most time consuming step in the design process, this severely reduces the advantages of high-level synthesis. This paper presents techniques and algorithms for comparing simulation results using the same simulation drivers. The approach is based on creating special hardware structures in the implementation and comparing the simulations only at synchronization points called "observable time windows".